
/* -*-C-*-
 ##############################################################################
 #
 # File:        trice/src/error.h
 # RCS:         "@(#)$Revision: 1.10 $ $Date: 94/03/08 11:20:05 $"
 # Description: header file for E1430 errors 
 # Author:      Doug Passey
 # Created:     
 # Language:    C 
 # Package:     E1430
 # Status:      "@(#)$State: Exp $"
 #
 # (C) Copyright 1992, Hewlett-Packard Company, all rights reserved.
 #
 ##############################################################################
 #
 # Revisions:
 #
 ##############################################################################
*/

#define ERR1430_ERROR_OFFSET			1000
#define ERR1430_MALLOC				1001
#define ERR1430_REALLOC				1002
#define ERR1430_NEW_STATE			1003
#define ERR1430_NO_MOD_AT_LA			1004
#define ERR1430_NO_GROUP			1005
#define ERR1430_ILLEGAL_MULTI_SYNC_MODE		1006
#define ERR1430_ILLEGAL_ADC_CLOCK_SOURCE	1007
#define ERR1430_ILLEGAL_DSP_CLOCK_SOURCE	1008
#define ERR1430_ILLEGAL_DATA_PORT		1009
#define ERR1430_ILLEGAL_PASS_TAG		1010
#define ERR1430_ILLEGAL_APPEND_STATUS		1011
#define ERR1430_ILLEGAL_DATA_TYPE		1012
#define ERR1430_ILLEGAL_DATA_SIZE		1013
#define ERR1430_ILLEGAL_BLOCKSIZE		1014
#define ERR1430_ILLEGAL_FILTER_PASS_MODE	1015
#define ERR1430_ILLEGAL_DECIMATE_MODE		1016
#define ERR1430_ILLEGAL_ANTI_ALIAS_MODE		1017
#define ERR1430_RANGE_OUT_OF_LIMITS		1018
#define ERR1430_ILLEGAL_INPUT_SOURCE		1019
#define ERR1430_ILLEGAL_DATA_MODE 		1020
#define ERR1430_TRIG_LINE_STATE			1021
#define ERR1430_ILLEGAL_COUPLING		1022
#define ERR1430_ILLEGAL_TRIGGER_MODE		1023
#define ERR1430_ILLEGAL_TRIGGER_SLOPE		1024
#define ERR1430_TRIG_LIN_LEVEL_RANGE		1025
#define ERR1430_TRIG_LOG_LEVEL_RANGE		1026
#define ERR1430_PRETRIGGER_GREATER_FIFO		1027
#define ERR1430_ILLEGAL_REGISTER_OFFSET		1028
#define ERR1430_ILLEGAL_INTR_NUMBER		1029
#define ERR1430_ILLEGAL_INTR_PRIORITY		1030
#define ERR1430_ILLEGAL_INTR_MASK 		1031
#define ERR1430_ILLEGAL_FILTER_BANDWIDTH	1032
#define ERR1430_WAIT_SYNC_TIMEOUT		1033
#define ERR1430_ONLY_ONE_MASTER			1034
#define ERR1430_ILLEGAL_SYNC_LINE_STATE		1035
#define ERR1430_UNABLE_TO_MAP_MEMORY		1036
#define ERR1430_UNABLE_TO_OPEN_SICL		1037
#define ERR1430_LA_NOT_IN_MOD_GROUP		1038
#define ERR1430_GROUP_NOT_CONTIGUOUS		1039
#define ERR1430_PARAMETER_UNEQUAL		1040
#define ERR1430_ILLEGAL_TRIG_BANDWIDTH		1041
#define ERR1430_TRIG_TIMEOUT			1042
#define ERR1430_ARM_TIMEOUT			1043
#define ERR1430_DATA_READ_TIMEOUT		1044
#define ERR1430_ILLEGAL_FILTER_BW		1045
#define ERR1430_ADC_ERROR			1046
#define ERR1430_AUTO_RANGE_MAX			1047
#define ERR1430_OPEN_STATEFILE			1048
#define ERR1430_READ_STATEFILE			1049
#define ERR1430_WRITE_STATEFILE			1050
#define ERR1430_CLOSE_STATEFILE			1051
#define ERR1430_NOT_STATEFILE			1052
#define ERR1430_MISMATCH_STATEFILE		1053
#define ERR1430_SYSTEM_TIME			1054
#define ERR1430_BUS_ERROR			1055
#define ERR1430_ILLEGAL_CLOCK_MASTER_MODE	1056
#define ERR1430_LOCAL_BUS_UNSUPPORTED		1057
#define ERR1430_LA_DECODE			1058
#define ERR1430_LA_TIMEOUT			1059
#define ERR1430_ILLEGAL_D32			1060
#define ERR1430_D8_TIMEOUT			1061
#define ERR1430_ILLEGAL_UNALIGNED_D16		1062
#define ERR1430_ILLEGAL_RESPONSE_A24		1063
#define ERR1430_ILLEGAL_RESPONSE_A32		1064
#define ERR1430_ILLEGAL_RESPONSE_REG		1065
#define ERR1430_ILLEGAL_WRITE_RESPONSE		1066
#define ERR1430_WRITE_TIMEOUT			1067
#define ERR1430_ILLEGAL_READ_RESPONSE		1068
#define ERR1430_NO_RESPONSE_DSP			1069
#define ERR1430_PORT_CONTROL_RW			1070
#define ERR1430_PORT_CONTROL_BAD		1071
#define ERR1430_SOFT_RESET_FAIL			1072
#define ERR1430_NO_SOFT_RESET			1073
#define ERR1430_TIMING_REG_RW			1074
#define ERR1430_STATUS_REG_READ			1075
#define ERR1430_IMPROPER_DSP_CLOCK		1076
#define ERR1430_MISSING_ADC_CLOCK		1077
#define ERR1430_IMPROPER_ADC_CLOCK		1078
#define ERR1430_MISSING_DSP_CLOCK		1079
#define ERR1430_REAL_DATA_16			1080
#define ERR1430_COMPLEX_DATA_16			1081
#define ERR1430_REAL_DATA_32			1082
#define ERR1430_COMPLEX_DATA_32			1083
#define ERR1430_MULTIPASS_DATA			1084
#define ERR1430_DECIMATION_PATTERN		1085
#define ERR1430_PASSTAG_24			1086
#define ERR1430_APPEND_STATUS			1087
#define ERR1430_NO_STATUS_BYTE			1088
#define ERR1430_INCORRECT_IDLE_EXIT		1089
#define ERR1430_FAIL_ENTER_TRIGGER		1090
#define ERR1430_FAIL_ENTER_MEASURE		1091
#define ERR1430_FAIL_ENTER_IDLE			1092
#define ERR1430_FAIL_ENTER_ARM			1093
#define ERR1430_FAIL_AUTO_TRIGGER		1094
#define ERR1430_FIFO_MEMORY_TEST		1095
#define ERR1430_ILLEGAL_TRIGGER_DELAY		1096
#define ERR1430_AUTO_ZERO_FAIL			1097
#define ERR1430_EXTRA_DATA_WORDS		1098
#define ERR1430_RESET_DSP			1099
#define ERR1430_VXI_INFO			1100
#define ERR1430_UNEXPECTED_INTERRUPT		1101
#define ERR1430_MISSING_ARMED_INTR		1102
#define ERR1430_MISSING_READ_VALID_INTR		1103
#define ERR1430_MISSING_BLOCK_READY_INTR	1104
#define ERR1430_MISSING_MEAS_DONE_INTR		1105
#define ERR1430_WRONG_INTR_STATUS		1106
#define ERR1430_NO_INTR_LINES			1107
#define ERR1430_INTERRUPT_INSTALL		1108
#define ERR1430_INTERRUPT_ENABLE 		1109
#define ERR1430_IOCTL_ERROR			1110
#define ERR1430_RS232_READ_ERROR		1111
#define ERR1430_OFFSET_DAC_BAD			1112
#define ERR1430_ILLEGAL_TRIG_EXIT		1113
#define ERR1430_FAIL_TRIG_EXIT			1114
#define ERR1430_FAIL_TRIG_DELAY			1115
#define ERR1430_WRONG_TRIG_SLOPE		1116
#define ERR1430_FAIL_TRIG_SLOPE			1117
#define ERR1430_REREAD_FAILURE			1118
#define ERR1430_ILLEGAL_LBUS_MODE		1119
#define ERR1430_ILLEGAL_LBUS_RESET		1120
#define ERR1430_SAMPLE_CLOCK_FREQ		1121
#define ERR1430_ILLEGAL_DATA_REREAD		1122
#define ERR1430_GROUP_NOT_LA			1123
#define ERR1430_NOT_SYNCHRONOUS_GROUP		1124
#define ERR1430_NO_MASTER			1125
#define ERR1430_ADC_OVERLOAD			1126
#define ERR1430_ILLEGAL_CLOCK_VALUE		1127
#define ERR1430_ILLEGAL_FILTER_SELECTION	1128
#define ERR1430_ILLEGAL_BUFFER_SIZE		1129
#define ERR1430_ILLEGAL_RESAMPLE OUTPUT RATI0	1130
#define ERR1430_LAST_ERROR_NUMBER		1130
